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2. Pipelining

Every CPU carries out the Fetch-Decode-Execute cycle. The idea of the pipeline is to stagger this cycle into three or more hardware processing paths within the CPU called a 'pipeline'.

At any given time, whilst a fetch operation is taking place on pipeline 1 which occupies the data and address buses, pipeline 2 is decoding an instruction and pipeline 3 is executing an instruction.

As long as the pipelines can be kept full, this is making maximum use of the CPU.

This kind of computer is classified as a Single Instruction Single Data computer or SISD